1. Field of the Invention
This invention relates to circuit testing and more specifically to built in self testing of digital to analog and analog to digital converters.
2. Description of the Prior Art
In testing Analog to Digital Converters (ADCs), and Digital to Analog Converters. (DACs), the following well known analog signal properties are of interest:
(1) gain--the slope of the best fit straight line which approximates the transfer function; PA1 (2) offset--the equivalent constant value added to all outputs, relative to the input; PA1 (3) noise--the random variations in the output for any signal input, or (small) random variations in the input-output transfer function; and PA1 (4) non-linearity--the differences between the transfer function and a straight line.
In many integrated circuits (ICs), both an ADC and DAC are present, to allow digital signal processing (DSP) of analog input signals and generation of an analog result. This is often called a "mixed signal" IC. The presence of both types of converters can facilitate the use of digital-only testing of these inherently mixed analog-digital functions: a digital stimulus can be applied to the DAC, the DAC's output connected to the ADC input, and the digital output signal compared to the expected result.
The primary problem with such a digital test solution is the intolerance of most digital tests to any bit errors. Whenever analog signals are used however, noise is inevitable, and the digital output of an ADC may occasionally be in error by one or two Least Significant Bits (LSBs). This is especially true for high precision (e.g. greater than 12 bits) or high speed (e.g. greater than 100 MHz) converters. Such errors are typically quite tolerable, because low-pass filtering will take place in the DSP or in the analog domain, both for anti-aliasing and for noise reduction.
In addition, analog output signals inevitably have some DC offset, which again is typically quite tolerable, because high-pass filtering is also used. In fact, high-pass filtering is often used in anticipation of DC offset which is only one of several inherent low frequency noise sources in any system.
Gain error can also be present and should be negligible, but in many systems a small (e.g. 1%-5%) gain error can be tolerated or compensated for. Even in high accuracy analog systems, better than 0.1% gain error is rare. For a 16-bit DAC, 0.1% amounts to 32 Least Significant Bits of error, at the maximum output.
Linearity is the most difficult non-ideal behavior to correct or tolerate. Non-linearity can cause harmonic distortion and intermodulation, both of which can cause problems, or are annoying to the human ear in an audio context. Differential non-linearity is the difference, at any point on the transfer function, between the actual voltage step size and the ideal step size corresponding to one LSB. In signal processing it causes noise, but only when an AC signal is present. Integral non-linearity is the peak difference between the actual transfer function and the best fit straight line. In signal processing, integral non-linearity causes harmonic distortion, and is more easily measured using a Fast Fourier Transform (FFT).
There are known all-digital test schemes that are supposedly noise tolerant. Almost all systems achieve noise-tolerance by low-pass filtering, which is a way of integrating the noise; integration causes averaging of the noise and the primary property of noise is that its average value is zero. In an all-digital approach, accumulating the error over time is the only way to integrate. This can be done by simply adding samples, or in a Discrete Fourier Transform (DFT).
One known testing approach applies a test signal from a binary counter or linear feedback shift register (LFSR) to the DAC and sums the resulting output signal from the ADC for all possible inputs, or a known subset thereof. Since noise on average sums to zero, the ADC output sum should be independent of noise. Unfortunately systematic errors such as offset are not "noise", so even a single LSB of offset causes the output sum to change dramatically. For example, one LSB offset increases the sum by 4096 (=2.sup.12) for a 12-bit system, masking any excessive noise or causing false rejection in testing of ICs with acceptable offset and noise. For a 12-bit DAC, with 5 volt range, an offset of only 10 mV is equivalent to 8 LSB, and so causes the sum to increase by greater than 32,000 (4096.times.8). Likewise a gain error will cause an error in the sum. A 1% gain error for a 12-bit system increases the sum by greater than 80,000 (0.5.times.1%.times.4096.times.4096). Although the acceptable range for the sum can be set accordingly, this might mask excessive noise or nonlinearity. To conclude, this method has the major drawback of providing only a composite test result, the composite being of gain, offset, noise, and linearity, and not testing for these parameters individually.
Methods have been proposed to minimize the amount of logic needed to accumulate the sum, by accumulating only the difference between the expected output and the actual output. Since the sum of the errors is ideally zero, a much smaller accumulator is needed. However, the above-mentioned fundamental flaws remain.
The typical prior art method to test ADCs and DACs in IC production is to apply a single frequency sinusoid as a test input signal, either in the analog domain or the digital equivalent. The resulting output signal is then processed using a DFT, to measure offset (0 Hz frequency component), gain (at the fundamental frequency), noise (standard deviation across all frequencies in bandwidth), and non-linearity (second and third harmonic components). This requires expensive off-chip test equipment (with an array processor) and special software. This method owes its precision to the fact that all analog samples (typically between 256 and 4096 samples) contribute to every measurement result and this extreme amount of redundancy minimizes the impact of isolated noise spikes or jitter.